Structural Hazards

A structural hazard occurs when a planned instruction (part) can not execute because the hardware does not support a certain combination of instructions to be executed simultaneously.

Again, imagine doing laundry. If you use a washer-dryer combination it would be impossible for you to execute your laundry pipeline. You you can not put new laundry in the washer after washing the first load, since it is used at the same time to dry the first load.
Therefore, the combination of the instruction "wash" followed by another "wash" is not supported by the hardware. This structural hazard would not occur if you have a seperate washer and dryer.

The RISC-V instruction set and corresponding datapaths are designed to be pipelined, which makes it easy to avoid having structural hazards. We have already seen some design decisions preventing structural hazards, like strictly separated datapath components suitable for stage separation or having different memories for instructions and data.

If there still occur such conflicts, the affected instruction can not execute and has to be delayed until there is a clock cycle in which the hardware is available for use again. Every clock cycle without a new instruction started is called a stall or "bubble", which illustrates the state of doing nothing.

Exercise

To give an example for a structural hazard, consider we designed our hardware to have only one memory for both instructions and data.
How many conflicts would occur due to conflicts caused by structural hazards, i. e. resource conflicts due to our memory hardware design choice?








How many clock cycles do we have to delay the sw instruction to solve the hazard?






CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9
To recall, with cleverly designed hardware we can avoid some stalls and reduce needed clock cycles. This prevents having to add additional control logic for monitoring certain instruction combinations.
Nevertheless, there are more types of hazards that only can be solved by looking more precisely at instruction combinations, as shown in the next chapters.