Welcome!
This page aims at providing an educational introduction to the design of
a pipelined processor hardware based on the RISC-V instruction set.
Knowledge about the underlying instruction set and basic concepts of
RISC-V is helpful to understand the content.
Ideally you use this website supplementary to a computer architecture
lecture, as this website was originally designed for this purpose.
The content elaborates on concepts covered by
Computer Organization and Design RISC-V Edition: The Hardware
Software Interface. This website
focusses on visualizing the fundamental elements of the processor
datapath and pipeline. It further tries to convey the reasoning behind
design decisions of a RISC-V processor, specifically when it comes to
hazard handling.
Structure
The content is divided in chapters. You can navigate through them using
the navigation at the top of the page or by following the links on the
bottom of every page linking to the next and previous chapters. In some
of the chapters you find exercises and annotations, highlighted in
boxes.
This website was developed as part of a Master's project in
collaboration with the Computer Architecture Chair at
Albert-Ludwigs-University of Freiburg, aimed at supporting the teaching
of the Computer Architecture lecture.