LRU Cache Visualization

Cache Model

This visualization demonstrates a simplified Cache with the following characteristics:

• Address width: 64 bits (only the bits 8 to 3 are shown for clarity -- we skip the 3 bits for the word offsets like in 64-bit RISC-V).
• Cache size: 2 sets, each with 4 ways (8 entries in total).
• Address split: [ Tag | Set | Word offset]. For simplicity the word offset will always be 0 (we do not consider unaligned memory accesses -- this is usually done by the memory controller who also combines the values after reading the cache).
• Replacement policy: Least Recently Used (LRU).
• No valid bit: All cache lines are assumed to be valid initially; therefore, there are no empty entries.

This model is intentionally simplified to focus on the fundamental behavior of set-associative caches. Advanced features such as write-back/write-through, valid bits, and dirty bits are not included.